The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
Manufacturing of semiconductor devices typically involves deposition of electrically conductive material on substrates such as semiconductor wafers. Physical vapor deposition (“PVD”) systems may be used to deposit metal layers on the substrate and/or to etch an exposed surface of the substrate.
The metal layers can be used as diffusion barriers, adhesion or seed layers, primary conductors, antireflection coatings, etch stops, etc. In some cases, the conductive material may be deposited by electroplating onto a seed layer of metal such as copper located in vias or trenches.
In PVD systems, plasma feed gas such as Argon is introduced into a chamber. Electrons collide with atoms of the plasma feed gas to create ions. Magnetic fields are used to increase a residence time of the electrons by causing the electrons to spiral through the plasma. As a result, ionization levels of the plasma feed gas also increase.
A negative potential applied to a cathode attracts the ions towards a target. The ions collide with the target. Target atoms are dislodged from the surface of the target by direct momentum transfer. The dislodged atoms and ions are then deposited on a substrate or used to etch the substrate.
The rates of etching or deposition can be adjusted by varying power applied to the target and an RF bias applied to the substrate. When the etch/deposition ratio is 1, no net deposition or etching is performed. When the E/D ratio is less than 1, net deposition occurs. When the E/D ratio greater than 1, net etching occurs.
Damascene processing may be used to form interconnections for integrated circuits (ICs). In a typical Damascene process, a pattern of trenches and/or vias is etched in a dielectric layer of a substrate. A thin layer of diffusion-barrier film is then deposited onto the dielectric layer. The diffusion barrier film may include a material such as tantalum (Ta), tantalum nitride (TaN), a TaN/Ta bilayer, or other suitable materials.
A seed layer of copper is deposited on the diffusion-barrier layer using PVD, CVD or another process. Afterwards, the trenches and vias are electroplated with copper. Finally, the surface of the wafer may be planarized to remove excess copper.
An etchback process may be used when creating the barrier/seed layer to improve the step coverage and/or barrier/seed layer performance. For example, etchback is used when depositing the diffusion barrier layer (such as TaN/Ta bilayer) to reduce the thickness of the barrier layer at the bottom of a dual damascene via. The reduced bottom coverage tends to reduce via resistance (Rc), improve distribution of the via resistance Rc and increase the resistance to electromigration.
There are several disadvantages associated with using the etchback process. Dielectric damage such as trench bottom roughening and microtrenching may occur. If a sloped surface exists in the structure (for example, a sloped surface in logic via chain structures), a higher resputtering yield at the sloped surface may cause little or no coverage or may even damage the dielectric (particularly at the sloped surface area).
Ultra-low k dielectric typically used for advanced nodes tends to be more susceptible to damage during the etchback process. Low plasma density (corresponding to high energetic ions under a particular RF bias power) typically used for etchback is responsible for the damage of the dielectric. One way to reduce the risk of dielectric damage is to lower the RF bias power. However, even with a low RF bias power, the energy of ions can still be high. Under the low density plasma conditions, the amount of ions available for etching is limited. Therefore, the risk of dielectric damage is still relatively high. Further lowering the RF bias will further reduce the resputter etch rate so the etch to deposition (E/D) ratio may be reduced to an unacceptable level for etching applications.
Furthermore, there are other disadvantages when using low E/D ratio etchback processes. The deposition component increases significantly and tends to cause overhang growth during the etchback process. The dielectric damage and increased overhang tends to adversely impact device yield and reliability.